Sigma-delta converters have become increasingly popular the last two decades. They are particularly useful in high-resolution, low-bandwidth applications, such as speech, audio, test, and measurement. Other types of converters, such as successive approximation, pipeline, and flash, are typically used in lower-resolution applications.
The marketplace for sigma-delta converters is growing exponentially, fueled by the availability of low cost digital-signal processing circuits. Unfortunately, limitations of current converter architectures mean that costly, high-power, low-performance switched-capacitor filters are used. Embodiments of the present invention allows the use of low-cost, low-power, continuous-time filters that enable sigma-delta converters to be used in a wider array of products and applications than is otherwise possible today.
FIG. 1 is a schematic of a conventional sigma-delta converter or modulator, also known as a delta-sigma, oversampling, or noise-shaping converter. These last two names are descriptive of the circuit""s operation. That is, a comparator 170 is oversampled at a rate much higher than the Nyquist rate of the input signal received on line 105. Also, the low frequency noise floor is reduced, while the high frequency noise is increased, such that the noise spectrum is xe2x80x9cshaped.xe2x80x9d The high frequency noise may be reduced by a low pass filter after the modulator.
Included are summing junctions 110 and 140, filters 130 and 160, digital-to-analog converters (DACs) 120 and 150, comparator 170, and optional delay and return-to-zero circuits 190 and 180. An input signal is received on line 105 by summing junction 110. An output of summing junction 110 is received by filter 130. Filter 130 is often a high-ordered filter, such as a fourth or sixth-order filter. An output of filter 130 is received by summing junction 140, which in turn drives a second filter 160. The construction of the second filter 160 may be similar to that of the first filter 130. The outputs of the second filter 160 drives the comparator 170, which provides an output on line 175. The comparator is clocked by a clocked signal received on clock line 172. This clock may be provided by a VCO, crystal, or other stable periodic source. The output of comparator 170 is applied to DACs 120 and 150, which in turn drive inverted inputs of summing junctions 110 and 140.
Several difficulties arise with this architecture. For example, if the comparator 170 is required to resolve a low level signal at its input, its output may become unstable. This metastability of the comparator output appears as jitter at the filter input, and thus reduces the converter""s performance. Also, any DAC ringing, settling time, or clock feedthrough similarly degrades performance. Accordingly, some prior art circuits have included either or both a return-to-zero 180 or delay element 190, such that the comparator decision points are removed in time from these DAC transients. Unfortunately, these fixes have limited success and cause other problems. For example, the inclusion of delay element 190 may make the converter unstable.
These problems have limited the use of continuous time or analog circuits for filters 130 and 160. Many applications use discrete-time signal processing techniques including switched capacitor filters for these blocks. Due to the oversampling requirements of the sigma-delta architecture, the switched-capacitor filters must run at several MHz even for audio applications. This makes the design of these filters difficult, and has limited their use at higher bandwidth applications. Moreover, as technology progresses to deep submicron processes, switched capacitor filters are becoming increasingly difficult to implement.
What is needed are methods and circuits that allow the use of continuous time or analog filters in sigma-delta converters, while addressing the comparator metastability, DAC settling, and clock feedthrough problems of the prior art.
Accordingly, embodiments of the present invention provide methods and circuits for using continuous-time filters that address comparator metastability, DAC settling, and clock feedthrough problems in sigma-delta converters.
A comparator output is delayed while a switch at the input of a continuous-time integrator or filter is opened. A DAC is driven by the delayed comparator output, and after the DAC output settles, the switch is closed, and the integrator reacts to the new DAC input.
An exemplary embodiment of the present invention provides a method of converting an analog signal to a digital signal. The method includes receiving the analog signal at a summing junction, receiving a clock signal transitioning between a first level and a second level, connecting an output of the summing junction to an integrator when the clock signal is at the first level, and disconnecting the output of the summing junction from the integrator when the clock signal is at the second level. The method also includes providing an output signal that is determined by the polarity of an output of the integrator when the clock signal transitions from the first level to the second level, delaying the output signal, receiving the delayed output signal with a digital-to-analog converter, and receiving an output of the analog-to-digital converter with the summing junction.
Another exemplary embodiment of the present invention provides an integrated circuit having an analog-to-digital converter. The analog-to-digital converter includes a summing junction having a non-inverting input configured to receive an analog signal, a continuous-time integrator, and a switch configured to receive a clock signal. The switch is connected between an output of the summing junction and an input of the continuous-time integrator. The integrated circuit also includes a comparator having an input connected to an output of the integrator, a delay element having an input coupled to an output of the comparator, and a digital-to-analog converter having an input coupled to an output of the delay element and an output coupled to an inverting input of the summing junction.
A further exemplary embodiment of the present invention provides a method of converting an analog signal to a digital signal. The method includes receiving the analog signal with a first summing junction and receiving a clock signal. The clock signal transitions between a first level and a second level. The method also includes coupling an output of the first summing junction to an input of a first integrator when the clock signal is at the first level, disconnecting the output of the first summing junction from the input of the first integrator when the clock signal is at the second level, receiving an output of the first integrator with a second summing node, coupling an output of the second summing junction to an input of a second integrator when the clock signal is at the first level, and disconnecting the output of the second summing junction from the input of the second integrator when the clock signal is at the second level. An output signal that is determined by the polarity of an output of the second integrator is provided when the clock signal transitions from the first level to the second level. The method also includes delaying the output signal, receiving the delayed output signal with a first digital-to-analog converter and a second digital-to-analog converter, receiving an output of the first digital-to-analog converter with the first summing junction, and receiving an output of the second digital-to-analog converter with the second summing junction.
Yet a further exemplary embodiment of the present invention provides an integrated circuit. This integrated circuit has an analog-to-digital converter, the analog-to-digital converter including a first summing junction coupled to an input terminal, a first switch coupled between the summing junction and a first continuous-time integrator, a second summing junction coupled to the first continuous-time integrator, and a second switch coupled between the second summing junction and a second continuous-time integrator. A comparator is coupled to the second continuous-time integrator and an output terminal, a first digital-to-analog converter is coupled between the comparator and the first summing node, and a second digital-to-analog converter is coupled between the comparator and the second summing node.
Still another exemplary embodiment of the present invention provides a method of converting an analog signal to a digital signal using a sigma-delta converter. The converter includes a summing junction, a continuous-time integrator coupled to a comparator, and a digital-to-analog converter coupled to the summing junction. The method includes receiving a clock signal. The clock signal transitions between a first level and a second level. The method also includes coupling the continuous-time integrator to the summing junction when the clock is at the first level, and disconnecting the continuous time integrator from the summing junction when the clock is at the second level.
A further exemplary embodiment of the present invention provides a method of converting an analog signal to a digital signal using a sigma-delta converter. The converter includes a first summing junction, a first continuous-time integrator coupled to a second summing junction, a second continuous-time integrator coupled to a comparator, a first digital-to-analog converter coupled to the first summing junction, and a second digital-to-analog converter coupled to the second summing junction. The method includes receiving a clock signal, where the clock signal transitions between a first level and a second level, coupling the first continuous-time integrator to the first summing junction and the second continuous-time integrator to the second summing junction when the clock is at the first level, and disconnecting the first continuous-time integrator from the first summing junction and the second continuous-time integrator from the second summing junction when the clock is at the second level.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.